This invention relates to a liquid crystal drive circuit and a liquid crystal display device using such a drive circuit.
In the liquid crystal display device, a liquid crystal drive circuit adapted for outputting a picture signal to drive the liquid crystal panel is used. The configuration of a drive circuit related to this invention is shown in FIG. 6. This drive circuit includes, every respective stages, sample hold circuits of the two latch system, and serves to carry out switching of hold operations of picture signals by using a signal given from the external of the chip.
For example, output circuits OC1-OC240 of 240 stages are disposed and respective output circuits OC1-OC240 are supplied with picture signals VIN. Further, hold switching signal CX is delivered from the external of the chip and is amplified by buffer composed of inverters IN2241 and IN 2242. Thereafter, the signal thus amplified is transferred through wiring W as hold switching signal CXD and is then delivered to respective output circuits OC1-OC240.
The output circuits OC1-OC240 respectively have the same configurations. Explanation will be given by taking the example of output circuit OC1. The output circuit OC1 includes a sample-hold circuit SH1, an amplifier AMP1 and an output terminal OUT1.
The sample-hold circuit SH1 includes a buffer composed of inverters IN2001a and IN2001b, a switching element SW1 composed of an N-channel type MOS transtor N1 and a P-channel type MOS transistor P1, a switching element SW2 composed of an N-channel type MOS transistor N2 and a P-channel type MOS transistor P2, a switching element SW3 composed of an N-channel type MOS transistor N3 and a P-channel type MOS transistor P3, a switching element SW4 composed of an N-channel type MOS transistor N4 and a P-channel type MOS transistor P4, and capacitors C1 and C2.
The inverter IN2001a is supplied with hold switching signal CXD to output hold switching signal CX1B. The inverter IN2001b is supplied with this hold switching signal CX1B to output hold switching signal CX1. The switching elements SW1 and SW2 are connected in series through node ND1, and the switching elements SW3 and SW4 are connected in series through node ND2 in a manner in parallel with these switching elements SW1 and SW2. Control signals A, /A, B, /B are respectively inputted to gates of transistors N1, P1, N3 and P3, and the above-mentioned hold switching signals CX1, CX1B, CX1B and CX1 are respectively inputted to gates of transistors N2, P2, N4 and P4. Thus, ON/OFF operations are controlled. In addition, the capacitor C1 is connected between the node ND1 and ground terminal and the capacitor C2 is connected between the node ND2 and ground terminal.
Output terminal ND3 of the sample-hold circuit SH1 is connected to the non-inverting input terminal of the amplifier AMP1. Output terminal of the amplifier AMP1 is connected to the inverting input terminal so that negative feedback loop is applied. The output terminal of the amplifier AMP1 is connected to output terminal OUT1. Thus, the same voltage as that of the node ND3 is outputted as output voltage OUT1.
The operation of the sample-hold circuit SH1 will now be described with reference to the time chart of FIG. 7 showing waveforms of respective signals. The hold switching signal CX inputted from the external is adapted so that switching between high level and low level is carried out every period of one cycle. This hold switching signal CX is inputted to respective output circuits OC1-OC240 through inverters IN2241 and IN2242. Thus, hold switching signals CXi (i is integer ranging from 1 to 240) which are the same as the signal CX in the logic level are generated by inverters IN2001a and IN2001b.
Picture signal VIN which takes voltage V0 at the cycle 1 and changes to voltage V1 in the process from the cycle 1 to the cycle 2 is inputted to the switching elements SW1 and SW3. The switching element SW1 is turned ON when control signal A in pulse form which takes high level at cycles 1, 3, 5 . . . is inputted thereto, and the switching element SW3 is turned ON by control signal B in pulse form which takes high level at cycles 2, 4, 6 . . .
At the cycle 1, the switching element SW1 is supplied with control signal A so that it is turned ON, but the switching element SW2 is supplied with hold switching signal CX1 of low level so that it is in OFF state. Thus, picture signal VIN of voltage V0 is passed through the switching element SW1. As a result, charges corresponding to voltage V0 of the node ND1 are stored into the capacitor C1. One switching element SW3 is maintained in OFF state. When the operation shifts to the next cycle 2, hold control signal CX of high level is delivered to the switching element SW2 so that it is turned ON. As a result, voltage V0 corresponding to charges stored in the capacitor C1 is produced from the node ND3, and is inputted to the amplifier AMP1.
At the cycle 2, the switching element SW1 is maintained in OFF state, the switching element SW3 is supplied with control signal B so that it is turned ON, and the switching element SW4 is placed in OFF state. Picture signal VIN having voltage V1 is passed through the switching element SW3. As a result, voltage (potential) of the node ND2 becomes equal to voltage V1. Thus, charges are stored into the capacitor C2. When the operation shifts to the next cycle, the switching element SW4 is turned ON. Thus, voltage V1 corresponding to charges of the capacitor C2 is produced at the node ND3, and is inputted to the amplifier AMP1.
In a manner as stated above, in respective output circuits OC1-OC240, voltages V0, V1, . . . are respectively outputted from the sample-hold circuits SH1. These voltages are outputted to the external as voltages OUT1-OUT240 through the amplifiers AMP1.
However, there were problems as described below in the liquid crystal drive circuit shown in FIG. 6. In FIG. 8, there is shown a circuit equivalent to the buffer composed of inverters IN2241, IN2242 supplied with hold switching signal CX, the signal line W for transferring hold switching signal CXD outputted from this buffer, and the output circuits OC1-OC240. These output circuits OC1-OC240 are arranged in row (parallel) because of restriction of wiring pattern on the chip. At the signal line W for transferring hold switching signal CXD, for a time period until that signal is inputted to the inverters IN within the respective output circuits OC1-OC240, there exist wiring resistors r0, r1, . . . , rn, . . . , rm, and parasitic capacitors C0, C1, . . . Cn, . . . , Cm.
When the hold switching signal CXD is passed through such wiring where wiring resistors and parasitic capacitors exist, waveforms of signals CXD1-CXD240 are caused to be waveform of which edge portions are gradually rounded as shown in FIG. 9. When such hold switching signals CXD1-CXD240 are inputted to inverters IN within the respective output circuits OC1-OC240, feed-through currents I (CXD1-CXD240) as shown in FIG. 9 are produced. According as rounding of the waveform of the signals CXD is developed, feed-through currents I (CXD) of the inverters IN are also increased. For this reason, in this circuit, there was the problem that power consumption is large.
Moreover, when the hold switching signal is transferred through the wiring W, the delay time of signal is short. For this reason, hold switching signal is delivered to all output circuits OC1-OC240 in the state where it is hardly delayed. Thus, switching elements carry out ON/OFF operations substantially at the same timing. As a result, noise followed by switching operation was superimposed on signal of the power supply line, resulting in the possibility that erroneous operation may take place.